View R4430PCF10MCM_13062.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

The Aeroflex "RISC TurboEngine"(c) A MIPS(c) R4400 RISC Microprocessor Multichip Module
(Preliminary Data Sheet, use with "MIPS R4000 Microprocessor Users Manual"(c) MIPS 1993) Aeroflex Circuit Technology 35 South Service Road, Plainview NY 11803 Tel:(516) 694-6700, Fax:(516) 694-6715
1.0 Description
The Aeroflex Circuit Technology "RISC TurboEngine" is a full military temperature range 64 bit, superpipelined RISC microprocessor with 1M Byte of secondary cache memory packaged in a high speed multichip module (MCM). The module contains the following components: * (1) R4400SC/MC, a 3.3V powered RISC microprocessor. * (11) SRAMs, 64K by 16. * (3) Buffers and (3) Passive components for phase lock loop operation. A Primary cache only version, the R4400PC is also available in the same package or 179 pin PGA
2.0 Flat Package Outline
"F10" Package
2.525 MAX 85 Spaces at 0.025 Pin 226 Pin 227 Pin 141 Pin 140
53 Spaces at 0.025
R4400PC/SC
MCM
Pin 87 Pin 86 .175 MAX
1.768 MAX .010
Pin 280 Pin 1
.072 .01
.006
Note: Outside ceramic tie bars not shown for clarity. Contact factory for details
1
SCD4430 Rev A 11/18/96
3.0 Electrical Features
* Low power dissipation, 3.3 Volt powered, 64 bit superpipelined RISC R4400 microprocessor - Highly integrated CPU with integer unit, FPA, MMU, I&D cache - Balanced integer & floating point performance - Exploits 2-level instruction-level parallelism - No issue restrictions on the instructions used * Integer unit - 32 entry, 64 bit wide register - ALU - Dedicated multiplier/divider * Super pipelined FPA - 32/16 entry 32/64 bit register file in a 32 bit mode - 32 entry 64 bit register file in 64 bit mode - Supports single and double precision. - Supports ANSI/IEEE Standard 754-1985 * Memory management unit - 48 entry TLB for fast virtual-to-physical address translation, software managed cntrl regstrs - Programmable page sizes from 4K bytes to 16M bytes - Total physical address space encompasses 64G bytes - One pair of pages per TLB entry, each programable in size from 4K bytes to 16M bytes * JTAG boundary scan capability for testing module interconnects. * Internal 1M byte secondary cache SRAM configured as a split cache with instruction and data sections separate. Can be factory configured as unified. * Provides 16 bit ECC on secondary cache data line, 7 bit ECC on tag line. * Minimum clock rate 50 mHz with no wait states. * +3.3 Volt P.S.(10 Watts Max.power dissipation) operation is standard.
4.0 Mechanical Features
* Small sizes, 2.5"L X 1.75"W X 0.175"H, 280 pin surface mount flat package or alternate 1.86"L X 1.86"W X 0.145"H, 179 pin PGA Package. * Full military operating temperature range of -55 C to +125 C, case temperature * Designed to meet military specifications, manufactured and tested in Aeroflex's MIL-PRF-38534 certified facility.
2
SCD4430 Rev A 11/18/96
5.0 INTERNAL BLOCK DIAGRAM(SC Version)
SCData(127:0) SCDchk(15:0) CE OE DQ143-DQ0 (9) 64K by 16 SRAMs A0 SCAddr0
SCDCS
SCOE
INTEGER EXECUTION UNIT General Registers ALU/Multiply/Divide Pipeline/Control CACHE/MMU 16K Byte 16K Byte Instruction Data Cache Cache Cache Control MMU
DATA/INSTRUCTION CACHE A14:A1 WE BWH A15 BWL
GND SCAddr (14:1)
48 Entry TLB
System Interface
FLOATING POINT FPU ALU BWH BWL A15 (2) 64K by 16 SRAMs OE CACHE TAG A14:A1 WE CE A0 DQ0-DQ31 SCTag(24:0) SCTchk(6:0) SCAddr 17 Multiply/Divide Square Root FP Register
Pipeline Control R4400SC/MC Microprocessor SCTCS SCWE
3
SCD4430 Rev A 11/18/96
6.0 Module Symbolic Interface Connections
R4400 Multichip Module
2 2
JTDI JTDO JTMS JTCK
TClock(1:0) RClock(1:0) MasterClock MasterOut SyncOut SyncIn IOOut IOIn Fault* VccP VssP Status(7:0) VccSense VssSense
Clock/Control Interface
Vcc Gnd
8
Note: Int(5:1)* available on R4400PC version IvdAck, IvdErr used in "MC" mode
4
SCD4430 Rev A 11/18/96
Power
JTAG Interface
SysAD(63:0) SysAD(7:0) SysCmd(8:0) SysCmdP ValidIn* ValidOut* ExtRqst* Release* RdRdy* WrRdy* IvdAck* IvdErr*
64 8 9
5
Int(5:1)* Int0* NMI*
System Interface
ModeClock ModeIn VCCOk ColdReset* Reset* 256K/1M*
Initialization Interface
Interrupt Interface
7.0 Signal Descriptions
System Interface Signals
SysAD(63:0) I/O System address/data bus: A 64 bit address and data bus for communication between the processor and an external agent System address/data check bus: An 8 bit bus containing check bits for the SysAD bus System command/identifier bus parity: A 9 bit bus for command and data identifier transmission between the processor and an external agent System command /data identifier bus parity: A single, even parity bit for thr SysCmd bus Valid Input: An external agent asserts ValidIn* when it is driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus Valid Output: The processor asserts ValidOut* when it is driving a valid address or data on the SysAD bus and a valid command or data identifier on the SYSCMD bus External Request: An external agent asserts ExtRqst* to request the use of the system interface. The processor grants the request by asserting Release* Release Interface: In response to the assertion of ExtRqst*, the processor asserts Release* to signal the requesting device that the system interface is available Read ready: The external agent asserts RdRdy*to indicate that it can accept processor read, invalidate, or update requests in both overlap and non-overlap mode or can accept a read followed by a potential invalidate or update request in the overlap mode Write ready: An external agent asserts WrRdy* when it can accept a processor write request Invalidate acknowledge: An external agent asserts IvdAck* to signal successful completion of a processor invalidate or update request (MC only) Invalidate error: An external agent asserts InvErr* to signal unsuccessful completion of a processor invalidate or update request(MC only)
SysADC(7:0) SysCmd(8:0)
I/O I/O
SysCmdP Validin*
I/O I
ValidOut*
O
ExtRqst*
I
Release*
O
RdRdy*
I
WrRdy* IvdAck*
I I
IvdErr*
I
5
SCD4430 Rev A 11/18/96
Clock/Control Interface Signals
TClock(1:0) RClock(1:0) MasterClock Masterout SyncOut O O I O O Transmit clocks : Two identical transmit clocks that establish the system interface frequency Receive clocks: Two identical receive clocks that establish the system interface frequency Master clock: Master clock input establishes the processor operating frequency Master clock out: Master clock output aligned with MasterClock Synchronization clock out: Synchronization clock output must be connected to SyncIn through an interconnect that models the interconnect between MasterOut, TClock, RClock, and the external agent. Synchronization clock in: Synchronization clock input I/O output: Output slew rate control feedback loop output. Must be connected to IOIn through a delay loop that models the I/O path from the processor to an external agent. I/O input: Output slew rate control feedback loop input (see IOOut) Fault: The processor asserts Fault to indicate a mismatch output of boundry comparators Quiet Vcc for the PLL: Quiet Vcc for the internal phase lock loop Quiet Vss for the PLL: Quiet Vss for the internal phase lock loop Status: An 8 bit bus that indicates the current operation status of the processor Vcc sense: This is a special pin used for testing and characterization. The voltage at this pin directly shows the behavior of the on chip Vcc. Vss sense: VssSense provides a separate, direct connection fron the on-chip Vss node to a package pin without attaching to the in-package ground planes. VssSence should be connected to Vss in functional system designs.
SyncIn IOOut
I O
IOIn Fault* VccP VssP Status(7:0) VccSense
I O I I O I/O
VssSense
I/O
6
SCD4430 Rev A 11/18/96
Interrupt Interface Signals: These signals comprise the interface used by
external agents to interrupt the R4400 processor Int(5:1)* I Interrupt: Five of six general processor interrupts, bitwise ORed with bits 5:1 of the interrupt register. This feature available on the R4400PC version only Interrupt: One of six general processor interrupts, bit wise ORed with bit 0 of the interrupt register Nonmaskable interrupt: Nonmaskable interrupt ORed with bit 6 of the interrupt register
Int0* NMI*
I I
Initialization Interface: These signals comprise the interface by which an
external agent initializes the R4400 operating parameters. ColdReset* I Cold Reset: This signal must be asserted for a power on reset or a cold reset. The clocks SClock, TClock, and RClock begin to cycle and are synchronized with the de-assertion edge of ColdReset*. ColdReset must be deasserted synchronously with MasterOut. Boot Mode Clock: Serial boot-mode data clock output at the system clock frequency divided by 256 Boot mode data in: Serial boot-mode data input. Reset: This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously for a cold reset, or synchronously to initate a warm reset. Reset must be de-asserted synchronously with MasterOut. Vcc is OK: When asserted, this signal tells the R4400 that the 3.3 Volt power supply has been above 3.15 Volts for more than 100 milliseconds & will remain stable . Assertion of VccOK starts initialization sequence. Cache size Select: Must be connected to ground to enable the full 1M Byte of cache. Cache size will be 256K if pin is left unconnected. JTAG data in: Data is serial, scanned in thru this pin JTAG clock input:The processor outputs a serial clock on JTCK. On the rising edge of JTCK, both JTDI and JTMS are sampled. JTAG data out: Data is serial, scanned out thru this pin JTAG: JTAG command signal indicates that the incomming serial data is command clear.
7
SCD4430 Rev A 11/18/96
ModeClock ModeIn Reset*
O I I
VccOk
I
256K/1M*
I
JTAG Interface Signals
JTDI JTCK I I
JTDO JTMS
O I
R4400SC/MC Microprocessor Multichip Module Pinouts Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Function TClock 0 Vss Sys AD 45 Vss TClock 1 Vss Sys AD 13 Vss Sys AD 14 Vcc JTMS Vcc Sys AD 46 Vcc JTDO Vcc Sys AD 15 Vcc Sys AD 47 Vss Status 0 Vcc JTDI Vss Sys ADC 1 Vcc Sys ADC 5 Vcc Status 2 Vcc Status 1 Vcc JTCK Vss Sync In Vss Vss Sense Vss Vcc Sense Vss MasterClock Vss Status 3 Vcc IvdErr* Vcc Status 4 Pin # 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 Function Vss VssP Vcc IvdAck* Vss VccP Vcc Status 5 Vss Status 6 Vcc Status 7 Vcc Sys ADC 7 Vcc Sys ADC 3 Vcc VCC Ok Vcc Sys AD 63 Vss MasterOut Vss Sys AD 31 Vcc Sys AD 30 Vcc Sys AD 62 Vss Sync Out Vss Sys AD 29 Vss RClock 1 Vss Sys AD61 Vss RClock 0 Vss Vcc Reset* Vcc Sys AD 60 Vss Sys AD 28 Vcc Cold_Reset* Pin # 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 Function Vss Sys AD 59 Vcc Sys AD 27 Vss IO In Vcc Sys AD 58 Vss Sys AD 26 Vcc IO Out Vss Sys AD 57 Vcc Sys AD 25 Vss GRPRUN 7 Vcc Sys AD 56 Vss Sys AD 24 Vcc GRPSTALL 3 Vss Sys ADC 6 Vcc Sys ADC 2 Vss NMI* Vcc Sys AD 55 Vss Sys AD 23 Vcc Release * Vss Sys AD 22 Vcc Sys AD 54 Vss Mode In Vcc Rd Rdy * Vss Sys AD 53 Sys AD 21
7 Do not connect, factory test only , 3 Connect to +V Volts
8
SCD4430 Rev A 11/18/96
Pin # 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188
R4400SC/MC Microprocessor Multichip Module Pinouts Function Pin # Function Pin # Vss 189 Int 4* 236 Ext RQST* 190 Vcc 237 Vcc 191 Int 5* 238 Sys AD 52 192 Vss 239 Vss 193 Vcc 240 Valid Out* 194 256K/1M* 241 Vcc 195 SPARE 242 Sys AD 20 196 SPARE 243 Vss 197 SPARE 244 Sys AD 19 198 CASE GROUND 245 Vcc 199 Vss 246 Sys AD 51 200 Sys AD 32 247 Vss 201 Vcc 248 ValidIn* 202 Sys AD 0 249 Vcc 203 Vss 250 Sys AD 18 204 Sys AD 1 251 Vss 205 Vcc 252 Sys AD 50 206 Sys AD 33 253 Vcc 207 Vss 254 InTO* 208 Sys AD 34 255 Vss 209 Vcc 256 Sys AD 49 210 Sys AD 2 257 Vcc 211 Vss 258 Sys AD 17 212 Sys Cmd 0 259 Vss 213 Vcc 260 Sys AD 16 214 Sys AD 35 261 Vcc 215 Vss 262 Sys AD 48 216 Sys AD 3 263 Vss 217 Vcc 264 SPARE 218 Sys AD 4 265 SPARE 219 Vss 266 SPARE 220 Sys Cmd 1 267 SPARE 221 Vcc 268 SPARE 222 Sys AD 36 269 SPARE 223 Vss 270 SPARE 224 Sys Cmd 2 271 Vss 225 Vcc 272 InT1* 226 Sys AD 5 273 Vcc 227 Sys AD 37 274 InT2* 228 Vss 275 Vss 229 Mode Clock 276 SPARE 230 Vcc 277 SPARE 231 WR RDY* 278 InT3* 232 Vss 279 SPARE 233 Sys AD 6 280 SPARE 234 Vcc Vss 235 Sys AD 38
Function Vss Sys Cmd 3 Vcc Sys AD 7 Vss Sys AD 39 Vcc Sys Cmd 4 Vss Sys ADC 0 Vcc Sys ADC 4 Vss Sys Cmd 5 Vcc Sys AD 8 Vss Sys AD 40 Vcc Sys Cmd 6 Vss Sys AD 9 Vcc Sys AD 41 Vss Sys CMD 7 Vcc Sys AD 10 Vss Sys AD 42 Vcc Sys Cmd 8 Vss Sys AD 11 Vcc Sys AD 43 Vss Sys Cmd P Vcc Sys AD 12 Vss Sys AD 44 Vcc Fault* Vss
9
SCD4430 Rev A 11/18/96
R4400PC -- PGA -- Pinouts (See Alternate Package Figure)
Function Coldreset ExtRqst Fault Reserved Vcc IOIn IOOut Int0 Intl Int2 Int3 Int4 lnt5 JTCK JTDI JTDO JTMS MasterClock MasterOut ModeClock ModeIn NMI PLLCap0 PLLCap1 RClock0 RClockl RdRdy Release Reset SyncIn SyncOut SysADO SysAD1 SysAD2 SysAD3 SysAD4 SysAD5 SysAD6 SysAD7 SysAD8 SysAD9 SysAD10 SysAD11 SysAD12 SysAD13
Pin # T14 U2 B16 U10 T9 T13 U12 N2 L3 K3 J3 H3 F2 H17 G16 F16 E16 J17 P17 B4 U4 U7 .... .... T17 R16 T5 V5 U16 J16 P16 J2 G2 El E3 C2 C4 B5 B6 B9 B11 C12 B14 B15 C16
Function SysAD14 SysAD15 SysAD16 SysAD17 Syr.AD18 SysAD19 SysAD20 SysAD21 SysAD22 SysAD23 SysAD24 SysAD25 SysAD26 SysAD27 SysAD28 SysAD29 SysAD30 SysAD31 SysAD32 SysAD33 SysAD34 SysAD35 SysAD36 SysAD37 SysAD38 SysAD39 SysAD40 SysAD41 SysAD42 SysAD43 SysAD44 SysAD45 SysAD46 SysAD47 SysAD48 SysAD49 SysAD50 SysAD51 SysAD52 SysAD53 SysAD54 SysAD55 SysAD56 SysAD57 SysAD58
Pin # D17 EIB K2 M2 Pi P3 T2 T4 U5 U6 U9 Ull T12 U14 U15 T16 R17 M16 H2 G3 F3 D2 C3 B3 C6 C7 C10 C11 B13 A15 C15 B17 E17 F17 L2 M3 N3 R2 T3 U3 T6 T7 T10 T11 U13
Function SysAD59 SysAD60 SysAD61 SysAD62 SysAD63 SysADC0 SysADC1 SysADC2 SysADC3 SysADC4 SysADC5 SysADC6 SysADC7 SysCmd0 SysCmd1 SysCmd2 SysCmd3 SysCmd4 SysCmd5 SysCmd6 SysCmd7 SysCmd8 SysCmd9 TClock0 TClockl VCCOk ValidIn ValidOut WrRdy VccP VssP Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc
Pin # V15 T15 U17 N16 N17 C8 G17 T8 L16 B8 H16 U8 L17 E2 D3 B2 A5 B7 C9 B10 B12 C13 C14 C17 D16 M17 P2 R3 C5 K17 K16 A2 A4 A9 A11 A13 A16 B18 C1 D18 Fl G18 Hl J18 K1
Function Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss
Pin # L18 M1 N18 R1 T18 Ul V3 V6 V8 V10 V12 V14 V17 A3 A6 A8 A10 A12 A14 A17 A18 B1 C18 D1 F18 GI H18 J1 K18 Ll M18 Nl P18 R18 Tl U18 V1 V2 V4 V7 V9 V11 V13 V16 V18
10
SCD4430 Rev A 11/18/96
ORDERING INFORMATION
Microprocessor Module Description R4430 Primary Cache, +3.3 Volt P.S. Flat Package R4430 Primary Cache, +3.3 Volt P.S. PGA Package R4430 1Meg Secondary Cache, +3.3 Volt P.S. Flat Package Part Number R4430PC F10 MCM R4430PC P10 MCM R4430SC 1M F10 MCM
Alternate Package Figure -- R4400PC -- PGA 179 Pins
"P10" Package
Bottom View
1 V U T R P N M L K J H G F E D C B A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Side View
.100 BSC
1.700 1.840 BSC 1.880
.018
1.700 BSC 1.840 1.880
.050 .221 MAX
Specification subject to change without notice 11
SCD4430 Rev A 11/18/96

▲Up To Search▲

Price & Availability of R4430PCF10MCM

	To Download R4430PCF10MCM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .